Bandgap reference circuit for providing reference voltage

ABSTRACT

A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed embodiments of the present invention relate to providing areference voltage, and more particularly, to a bandgap reference circuitcapable of providing a reference voltage having a voltage level below,for example, 1.25V.

2. Description of the Prior Art

A voltage reference generator is an essential design block required inanalog and mixed circuits, such as data converters, phase lock-loops(PLL), oscillators, power management circuits, dynamic random accessmemory (DRAM) and flash memories. A voltage reference generatortypically employs a bandgap reference circuit to generate a bandgapreference that is relatively insensitive to temperature, power supplyand load variations.

Please refer to FIG. 1, which is a schematic diagram of an exemplaryexample of a conventional bandgap reference circuit 100. Theconventional bandgap reference circuit 100 includes a transistor 110, aresistor 120 and a diode 130. The transistor 110 has a first connectionnode N1, a second connection node N2 and a control node NC. The resistor120 has a first end E1 and a second end E2. The diode 130 has an anodeand a cathode. The first connection node N1 of the transistor 110 iscoupled to a supply voltage VDD, the second connection node N2 of thetransistor 110 is coupled to the first end E1 of the resistor 120, andthe control node NC of the transistor 110 is coupled to a bias voltageVBS. The second end E2 of the resistor 120 is coupled to the anode ofthe diode 130. The cathode of the diode 130 is coupled to an electricalground GND.

The bias voltage VBS controls the transistor 110 to be enabled, therebygenerating a proportional-to-absolute-temperature current I_(PTAT). Ifthe value of the resistor 120 is R0, a cross voltage I_(PTAT)×R will beyielded when the current I_(PTAT) passes through the resistor 120. Inthis way, an output voltage V_(out) of the bandgap reference circuit 100may be expressed as follows: V_(out)=V_(BE)+I_(PTAT)×R0, wherein thevoltage V_(BE) is the forward bias voltage of the diode 130.

Since the voltage V_(BE) is the forward bias voltage of the diode 130,the voltage V_(BE) has a negative temperature coefficient. That is, thevoltage V_(BE) decreases in response to temperature increase, or viceversa. Similarly, the cross voltage I_(PTAT)×R has a positivetemperature coefficient due to the electrical characteristics of boththe transistor 110 and the resistor 120. As a result, the output voltageV_(out) of the bandgap reference circuit 100 may be immune totemperature variations when the voltage V_(BE) complements the crossvoltage.

The reference voltage outputted from a conventional bandgap referencecircuit is usually about 1.25V, however, which is roughly equal tosilicon bandgap energy measured at 0K in electron volts, whereas recentIC design typically requires operation regions below 1.25V. Thus, thereis a need for an innovative bandgap reference circuit capable ofproviding a lower reference voltage.

SUMMARY OF THE INVENTION

In accordance with exemplary embodiments of the present invention, abandgap reference circuit capable of providing a reference voltagehaving a voltage level below, for example, 1.25V is proposed to solvethe above-mentioned problem.

According to a first aspect of the present invention, an exemplarybandgap reference circuit is disclosed. The exemplary bandgap referencecircuit includes a first circuit, a second circuit and a third circuit.The first circuit is for generating a first current and a first voltageaccording to a first reference voltage. The second circuit is coupled tothe first circuit, for generating a second voltage according to thefirst voltage. The third circuit is coupled to the first circuit and thesecond circuit, for generating a voltage offset according to the firstcurrent, and generating a bandgap reference voltage according to thesecond voltage and the voltage offset. The first circuit and the secondcircuit complement each other for offsetting variations of the bandgapreference voltage due to temperature changes.

According to a second aspect of the present invention, an exemplarybandgap reference circuit is disclosed. The exemplary bandgap referencecircuit includes a proportional-to-absolute-temperature (PATA) circuit,a complementary-to-absolute-temperature (CATA) circuit and an outputcircuit. The PATA circuit is for generating a PATA voltage according toa first reference voltage. The CATA circuit is coupled to the PATAcircuit, for generating a CATA voltage. The output circuit is coupled tothe PATA circuit and the CATA circuit, for generating a bandgapreference voltage according to the PATA voltage and the CATA voltage;

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an exemplary example of a conventionalbandgap reference circuit.

FIG. 2 is a schematic diagram of a bandgap reference circuit accordingto an exemplary embodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should be interpreted to mean “include, but notlimited to . . . .” Also, the term “couple” is intended to mean eitheran indirect or direct electrical connection. Accordingly, if one deviceis electrically connected to another device, that connection may bethrough a direct electrical connection, or through an indirectelectrical connection via other devices and connections.

Please refer to FIG. 2, which is a schematic diagram of a bandgapreference circuit according to an exemplary embodiment of the presentinvention. The bandgap reference circuit 200 includes, but is notlimited to, a first circuit 210, a second circuit 220 and a thirdcircuit 230. The first circuit 210 is used as a current source forgenerating an initial proportional-to-absolute-temperature currentI_(PTAT) and a voltage V_(BE1) according to a reference voltage VBS. Thesecond circuit 220 is coupled to the first circuit 210, and used as avoltage divider for generating a divided voltage V_(BE1)′ according tothe voltage V_(BE1). The third circuit 230 is coupled to the firstcircuit 210 and the second circuit 220, and used for generating avoltage offset ΔV according to a mirrored current I_(PTAT)′, andgenerating a bandgap reference voltage V_(ref) according to the dividedvoltage V_(BE1)′ and the voltage offset ΔV. Further details of the firstcircuit 210, the second circuit 220 and the third circuit 230 aredescribed in the following.

By way of example, the first circuit 210 may include, but is not limitedto, a differential amplifier 212, a plurality of transistors (e.g. PMOStransistors) P₁ and P₂, a resistor R₁, and a plurality of diodes Q₁ andQ₂. The differential amplifier 212 has a positive input node (+), anegative input node (−) and an output node N_(OUT). Each of thetransistors P₁ and P₂ has a first connection node (e.g. a sourceterminal) N1, a second connection node (e.g. a drain terminal) N2 and acontrol node (e.g. agate terminal) NC. The resistor R₁ has a first endE1 and a second end E2. Each of the diodes Q₁ and Q₂ has an anode and acathode. The first connection node N1 of the transistor P₁ is coupled toa supply voltage VDD, the second connection node N2 of the transistor P₁is coupled to the positive input node (+) of the differential amplifier212, and the control node NC of the transistor P₁ is coupled to theoutput node N_(OUT) of the differential amplifier 212. The firstconnection node N1 of the transistor P₂ is coupled to the supply voltageVDD, the second connection node N2 of the transistor P₂ is coupled tothe negative input node (−) of the differential amplifier 212, and thecontrol node NC of the transistor P₂ is coupled to the output nodeN_(OUT) of the differential amplifier 212. The first end E1 of theresistor R₁ is coupled to the negative input node (−) of thedifferential amplifier 212. The anode of the diode Q₁ is coupled to thepositive input node (+) of the differential amplifier 212, and thecathode of the diode Q₁ is coupled to an electrical ground GND. Theanode of the diode Q₂ is coupled to the second end E2 of the resistorR₁, and the cathode of the diode Q₂ is coupled to the electrical groundGND. This is for illustrative purposes only, however, and not meant tobe a limitation of the present invention. In a modification of the abovecircuit, the diodes Q₁ and Q₂ may be substituted with bipolar junctiontransistors (BJTs) in a forward-biased configuration.

By way of example, the second circuit 220 may include, but is notlimited to, a differential amplifier 222, a transistor (e.g. a PMOStransistor) P₃, and a plurality of resistors R₂ and R₃. The differentialamplifier 222 has a positive input node (+), a negative input node (−)and an output node N_(OUT). The transistor P₃ has a first connectionnode N1, a second connection node N2 and a control node NC. Each of theresistors R₂ and R₃ has a first end E1 and a second end E2. The positiveinput node (+) of the differential amplifier 222 is coupled to thenegative input node (−) of the differential amplifier 212 for receivingthe voltage V_(BE1). The first connection node N1 of the transistor P₃is coupled to the supply voltage VDD, the second connection node N2 ofthe transistor P₃ is coupled to the negative input node (−) of thedifferential amplifier 222, and the control node NC of the transistor P₃is coupled to the output node N_(OUT) of the differential amplifier 222.The first end E1 of the resistor R₂ is coupled to the negative inputnode (−) of the differential amplifier 222. The first end E1 of theresistor R₃ is coupled to the second end E2 of the resistor R₂, and thesecond end E2 of the resistor R₃ is coupled to the electrical groundGND. Please note this is for illustrative purposes rather than alimitation of the present invention. Since the primary operation of thesecond circuit 220 is to “copy” the voltage V_(BE1) and to divide thevoltage V_(BE1), the second circuit 220 may be implemented with avoltage follower and a voltage divider, as long as the employed voltagefollower and voltage divider are relatively insensitive to temperaturevariations.

By way of example, the third circuit 230 may include, but is not limitedto, a differential amplifier 232, a plurality of transistors P₄ and P₅,and a plurality of resistors R₄ and R₅. The differential amplifier 232has a positive input node (+), a negative input node (−) and an outputnode N_(OUT). Each of the transistors P₄ and P₅ has a first connectionnode N1, a second connection node N2 and a control node NC. Each of theresistors R₄ and R₅ has a first end E1 and a second end E2. The positiveinput node (+) of the differential amplifier 232 is coupled to thesecond end E2 of the resistor R₂ for receiving the voltage V_(BE1)′. Thefirst connection node N1 of the transistor P₄ is coupled to the supplyvoltage VDD, the second connection node N2 of the transistor P₄ iscoupled to the negative input node (−) of the differential amplifier232, and the control node NC of the first transistor P₄ is coupled tothe output node N_(OUT) of the differential amplifier 232. The firstconnection node N1 of the transistor R₅ is coupled to the supply voltageVDD, and the control node NC of the transistor R₅ is coupled to theoutput node N_(OUT) of the differential amplifier 212 for receiving thebias voltage VBS from the first circuit 210. In other words, thetransistors P₁, P₂ and P₃ will be biased by the same gate voltage. Thefirst end E1 of the resistor R₄ is coupled to the second connection nodeN2 of the second transistor R₅, and the second end E2 of the resistor R₄is coupled to the negative input node (−) of the differential amplifier232. The first end E1 of the resistor R₅ is coupled to the second end E2of the resistor R₄, and the second end E2 of the resistor R₅ is coupledto the electrical ground GND. This is for illustrative purposes only,however, and is not meant to be a limitation of the present invention.Since the transistor R₄ merely serves as a load on the feedback path ofthe differential amplifier 232, the transistor P₄ may be replaced with aresister or other kinds of loads.

In this embodiment shown in FIG. 2, the output node N_(OUT) of thedifferential amplifier 212 outputs the reference voltage VBS which isused to control conductivity of the transistors P₁ and P₂. Thetransistors P₁ and P₂ serve as a current follower in order to generatethe current I_(PTAT). Specifically, the differential amplifier 212 isused to adjust the bias voltage of the transistors P₁ and P₂ each timethere is a discrepancy between voltages at the positive input node (+)and the negative input node (−), thereby stabilizing the referencevoltage VBS at the output node N_(OUT). In this way, the currentI_(PTAT) generated by the first circuit 210 will have a positivetemperature coefficient due to the electrical characteristics of thetransistor P₂; that is, the current I_(PTAT) increases along with thetemperature. Hence, the first circuit 210 may be regarded as aproportional-to-absolute-temperature (PTAT) circuit. The voltage V_(BE1)is then yielded by the current I_(PTAT) passing through the resistor R₁.Specifically, a cross voltage I_(PTAT)×R₁ will be yielded when thecurrent I_(PTAT) passes through the resistor R₁. In this way, thevoltage at the negative input node (−) may be expressed as follows:V_(BE1)=V_(BE)+I_(PTAT)×R₁, where the voltage V_(BE) is the forward biasvoltage of the diode Q₂. Please note that the transistors P₁ and P₂should be matched in order to accurately follow the current I_(PTAT).

The voltage V_(BE1) received at the positive input node (+) of thedifferential amplifier 222 is introduced to the negative input node (−)of the differential amplifier 222 due to a negative feedbackconfiguration of the differential amplifier 222. Specifically, whenthere is a discrepancy between voltages at the positive input node (+)and negative input node (−) of the differential amplifier 222, thedifferential amplifier 222 adjusts the bias voltage provided to thecontrol node NC of the transistor P₃ for increasing/decreasing thecurrent passing through the transistor P₃ and the resistors R₂ and R₃,thereby forcing the voltage at the negative input node (−) of thedifferential amplifier 222 to follow the voltage (i.e. V_(BE1)) at thepositive input node (+) of the differential amplifier 222. The voltageV_(BE1) introduced at the negative input node (−) of the differentialamplifier 222 is then fed into a voltage divider constituted by theresistors R₂ and R₃. In a case where (R₂+R₃)/R₃=A, the divided voltageV_(BE1)′ is equal to the voltage V_(BE1) divided by the ratio A. Thevoltage V_(BE1)′ generated via the voltage V_(BE1) will have a negativetemperature coefficient since the resistors R₂ and R₃ have asmall/negligible temperature dependency, and the voltage V_(BE1) has anegative temperature coefficient. That is, the voltage V_(BE1)′decreases while the temperature increases. The second circuit 220 may beregarded as a complementary-to-absolute-temperature (CATA) circuit.

In addition, the transistor P₅ serves as a current mirror which mirrorsthe current I_(PTAT), and the mirrored current I_(PTAT)′ passes throughthe resistor R₄, thereby yielding the voltage offset ΔV. In equationform, ΔV=I_(PTAT)×R₄=I_(PTAT)×R₀/A. In this embodiment, the resistancevalue of the resistor R₄ is equal to the resistance value of theresistor R₀ divided by the ratio A (i.e., R₄=R₀/A). R₀ is the resistanceof resistor 120. The voltage V_(BE1)′ received at the positive inputnode (+) of the differential amplifier 232 is introduced to the negativeinput node (−) of the differential amplifier 232 due to a negativefeedback configuration of the differential amplifier 232. Specifically,when there is a discrepancy between voltages at the positive input node(+) and negative input node (−) of the differential amplifier 232, thedifferential amplifier 232 adjusts the bias voltage provided to thecontrol node NC of the transistor P₄ for increasing/decreasing thecurrent passing through the transistor P₄, thereby forcing the voltageat the negative input node (−) of the differential amplifier 232 tofollow the voltage (i.e., V_(BE1)′) at the positive input node (+) ofthe differential amplifier 232. The third circuit 230 may be regarded asan output circuit which combines the voltage offset ΔV and the voltageV_(BE1)′ in order to output the bandgap reference voltage V_(ref). Inequation form,V_(ref)=V_(BE1)′+ΔV=V_(BE1)/A+I_(PTAT)×R₀/A=(V_(BE1)+I_(PTAT)×R₀)/A.Compared to the conventional design which generates a reference voltageV_(out)=V_(BE)+I_(PTAT)×R, the proposed design is capable of providing alower bandgap reference voltage V_(ref) by properly setting the ratio A.

Please note that only the transistors P₅ and P₂ are required to bematched in order to accurately mirror the current I_(PTAT)′ from thecurrent I_(PTAT) while the transistors P₃ and P₄ do not need to matchother transistors. This greatly simplifies the implementation of thebandgap reference circuit 200.

In short, the spirit of the present invention is to combine a CATAvoltage (e.g. the voltage V_(BE1)′) and a PATA voltage (e.g. the voltageoffsetΔV), in order to generate a temperature insensitive bandgapreference voltage. Since the CATA voltage and the PATA voltage are bothscaled by the ratio A, the bandgap reference voltage may be controlledbelow 1.25V. Therefore, the proposed bandgap reference circuit 200 iscapable of providing a reference voltage below 1.25V to meet therequirements of an application with an operation region below 1.25V.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A bandgap reference circuit, comprising: a firstcircuit, for generating a first current and a first voltage according toa first reference voltage; a second circuit, coupled to the firstcircuit, for generating a second voltage according to the first voltage;and a third circuit, coupled to the first circuit and the secondcircuit, for generating a voltage offset according to the first current,and generating a bandgap reference voltage according to the secondvoltage and the voltage offset; wherein the first circuit and the secondcircuit complement each other for offsetting variations of the bandgapreference voltage due to temperature changes; wherein the third circuitcomprises: a first differential amplifier, having a positive input node,a negative input node and an output node, the positive input node of thefirst differential amplifier for receiving the second voltage generatedfrom the second circuit; a first transistor, having a first connectionnode, a second connection node and a control node, the second connectionnode of the first transistor is coupled to the negative input node ofthe first differential amplifier, the first connection node of the firsttransistor is coupled to the first reference voltage, and the controlnode of the first transistor is coupled to the output node of the firstdifferential amplifier; a second transistor, having a first connectionnode, a second connection node and a control node, the first connectionnode of the second transistor is coupled to the first reference voltage,and the control node of the second transistor is for receiving a biasvoltage from the first circuit; a first resistor, having a first end anda second end, the first end of the first resistor is coupled to thesecond connection node of the second transistor, and the second end ofthe first resistor is coupled to the negative input node of the firstdifferential amplifier; and a second resistor, having a first end and asecond end, the first end of the second resistor is coupled to thesecond end of the first resistor, and the second end of the secondresistor is coupled to a second reference voltage; wherein the secondcircuit comprises: a second differential amplifier, having a positiveinput node, a negative input node and an output node, the positive inputnode of the second differential amplifier for receiving the firstvoltage generated from the first circuit; a third transistor, having afirst connection node, a second connection node and a control node, thesecond connection node of the third transistor is coupled to thenegative input node of the second differential amplifier, the firstconnection node of the third transistor is coupled to the firstreference voltage, and the control node of the third transistor iscoupled to the output node of the second differential amplifier; a thirdresistor, having a first end and a second end, the first end of thethird resistor is coupled to the negative input node of the seconddifferential amplifier, the second end of the third resistor is coupledto the positive input node of the first differential amplifier; and afourth resistor, having a first end and a second end, the first end ofthe fourth resistor is coupled to the second end of the third resistor,and the second end of the fourth resistor is coupled to the secondreference voltage; wherein the first circuit comprises: a thirddifferential amplifier, having a positive input node, a negative inputnode and an output node, the negative input node of the thirddifferential amplifier is coupled to the positive input node of thesecond differential amplifier, and the output node of the thirddifferential amplifier is coupled to the control node of the secondtransistor; a fourth transistor, having a first connection node, asecond connection node and a control node, the first connection node ofthe fourth transistor is coupled to the first reference voltage, thesecond connection node of the fourth transistor is coupled to thepositive input node of the third differential amplifier, and the controlnode of the fourth transistor is coupled to the output node of the thirddifferential amplifier; a fifth transistor, having a first connectionnode, a second connection node and a control node, the second connectionnode of the fifth transistor is coupled to the negative input node ofthe third differential amplifier, the first connection node of the fifthtransistor is coupled to the first reference voltage, and the controlnode of the fifth transistor is coupled to the output node of the thirddifferential amplifier; a fifth resistor, having a first end and asecond end, the first end of the fifth resistor is coupled to thenegative input node of the first differential amplifier; a first diode,having an anode and a cathode, the anode of the first diode is coupledto the positive input node of the third differential amplifier, and thecathode of the first diode is coupled to a second reference voltage; anda second diode, having an anode and a cathode, the anode of the seconddiode is coupled to the second end of the fifth resistor, and thecathode of the second diode is coupled to the second reference voltage.2. The bandgap reference circuit of claim 1, wherein the first circuitis a proportional-to-absolute-temperature (PATA) circuit.
 3. The bandgapreference circuit of claim 1, wherein the second circuit is acomplementary-to-absolute-temperature (CATA) circuit.
 4. The bandgapreference circuit of claim 1, wherein the first reference voltage islower than 1.25 volts.
 5. A bandgap reference circuit, comprising: aproportional-to-absolute-temperature (PATA) circuit, for generating aPATA voltage according to a first reference voltage; acomplementary-to-absolute-temperature (CATA) circuit, coupled to thePATA circuit, for generating a CATA voltage; and an output circuit,coupled to the PATA circuit and the CATA circuit, for generating abandgap reference voltage according to the PATA voltage and the CATAvoltage; wherein the output circuit comprises: a first differentialamplifier, having a positive input node, a negative input node and anoutput node, the positive input node of the first differential amplifierfor receiving the CATA voltage generated from the CATA circuit; a firsttransistor, having a first connection node, a second connection node anda control node, the second connection node of the first transistor iscoupled to the negative input node of the first differential amplifier,the first connection node of the first transistor is coupled to thefirst reference voltage, and the control node of the first transistor iscoupled to the output node of the first differential amplifier; a secondtransistor, having a first connection node, a second connection node anda control node, the first connection node of the second transistor iscoupled to the first reference voltage, and the control node of thesecond transistor is for receiving a bias voltage from the PATA circuit;a first resistor, having a first end and a second end, the first end ofthe first resistor is coupled to the second connection node of thesecond transistor, and the second end of the first resistor is coupledto the negative input node of the first differential amplifier; and asecond resistor, having a first end and a second end, the first end ofthe second resistor is coupled to the second end of the first resistor,and the second end of the second resistor is coupled to a secondreference voltage; wherein the CATA circuit comprises: a seconddifferential amplifier, having a positive input node, a negative inputnode and an output node, the positive input node of the seconddifferential amplifier for receiving the first voltage generated fromthe first circuit; a third transistor, having a first connection node, asecond connection node and a control node, the second connection node ofthe third transistor is coupled to the negative input node of the seconddifferential amplifier, the first connection node of the thirdtransistor is coupled to the first reference voltage, and the controlnode of the third transistor is coupled to the output node of the seconddifferential amplifier; a third resistor, having a first end and asecond end, the first end of the third resistor is coupled to thenegative input node of the second differential amplifier, and the secondend of the third resistor is coupled to the positive input node of thefirst differential amplifier; and a fourth resistor, having a first endand a second end, the first end of the fourth resistor is coupled to thesecond end of the third resistor, and the second end of the fourthresistor is coupled to the second reference voltage; wherein the PATAcircuit comprises: a third differential amplifier, having a positiveinput node, a negative input node and an output node, the negative inputnode of the third differential amplifier is coupled to the positiveinput node of the second differential amplifier, and the output node ofthe third differential amplifier is coupled to the control node of thesecond transistor; a fourth transistor, having a first connection node,a second connection node and a control node, the first connection nodeof the fourth transistor is coupled to the first reference voltage, thesecond connection node of the fourth transistor is coupled to thepositive input node of the third differential amplifier, and the controlnode of the fourth transistor is coupled to the output of the thirddifferential amplifier; a fifth transistor, having a first connectionnode, a second connection node and a control node, the first connectionnode of the fifth transistor is coupled to a negative input node of thethird differential amplifier, the second connection node of the fifthtransistor is coupled to the first reference voltage, and the controlnode of the fifth transistor is coupled to the output node of the thirddifferential amplifier; a fifth resistor, having a first end and asecond end, the first end of the fifth resistor is coupled to thenegative input node of the first differential amplifier; a first diode,having an anode and a cathode, the anode of the first diode is coupledto the positive input node of the third differential amplifier, and thecathode of the first diode is coupled to a second reference voltage; anda second diode, having an anode and a cathode, the anode of the seconddiode is coupled to the second end of the fifth resistor, and thecathode of the second diode is coupled to the second reference voltage.6. The bandgap reference circuit of claim 5, wherein the first referencevoltage is lower than 1.25 volts.